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Judge Andrews Construes Terms of Logic Circuit Patents

Judge Andrews has issued his memorandum opinion construing disputed terms of four patents related to logic and memory circuits for integration into high density integrated circuit chips. In 2011, the plaintiffs, HSM Portfolio and Technology Properties Limited, filed an infringement suit against eighteen defendants, of which eight remain in the case. After oral argument on June 5, Judge Andrews issued his construction of the following terms on June 17:
– “the N-channel field effect transistor in each inverter stage having a channel width which is less than a [predetermined factor] times the width of the N-channel of the immediately preceding inverter stage”
– “wherein the N-channel field effect transistor in the first inverter stage has a channel width which is less than said [predetermined factor] times the width of the at least one N-channel field effect transistor in the logic gate”
– “[the P-channel field effect transistor in each inverter stage having a channel which is wider than the channel of the corresponding N-channel field effect transistor of each inverter stage by ƞ], the ratio of electron mobility in the N-channel field effect transistors to hole mobility in the P-channel field effect transistors”
– “[A Field Effect Transistor (PET) Differential Latching Inverter (DLI) circuit] for sensing signals on first and second bit lines of a memory”
– “first and second bit lines of a memory”
– “first bit line” / “second bit line”
– “an inverter transfer function … which is identical when said first and second inverters turn on and turn off”
– “the outputs of said first and second complementary FET inverters producing output signals for said DLI circuit”
– “for receiving [a logic input signal/a clock input signal]”
– “A field effect transistor (FET) logic circuit comprising”
– “the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said first conductivity type being [substantially greater than] the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said second conductivity type”
– “for receiving [logic input signals]”
HSM Portfolio LLC, et al. v. Fujitsu Limited, et al., C.A. No. 11-770-RGA, Memo. Op. at 1-15 (D. Del. June 17, 2014).

HSM Portfolio LLC, et al. v. Fujitsu Limited, et al., C.A. No. 11-770-RGA (D. Del. June 17, 2014).

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